1. Field of the Invention
The present invention relates generally to signal comparators and more particularly to comparators that are realized with complementary metal-oxide semiconductor (CMOS) processes.
2. Description of the Related Art
FIG. 1 illustrates a comparator 18 that includes a differential pair 22 which receives current from a current source 24. The differential pair 22 is formed of transistors 26 and 28 whose gates and drains are respectively coupled to a comparator input port 30 and a comparator output port 32. The drains of the transistors 26 and 28 are provided with active loads in the form of current mirrors 36 and 38.
In particular, the current mirrors 36 and 38 are cross coupled to the transistors 26 and 28 so that each has an input that responds to a current from a respective one of these transistors and an output that mirrors current to the other. The current mirrors act as current latches to provide positive feedback and to discharge parasitic capacitances associated with the mirror transistors of the current mirrors 36 and 38 and the output port 32.
The conventional comparator 18 has been described in various references (e.g., U.S. Pat. No. 5,274,275 issued Dec. 28, 1993 to Coles, Joseph H. and U.S. Pat. No. 5,369,319 issued Nov. 24, 1994 to Good, Brian K., et al.). It is formed with complementary metal-oxide semiconductor (CMOS) transistors which each have a conductive gate and a channel that are separated by an oxide layer.
This structure is the source of a capacitance that is equally split between a gate-to-source capacitance and a gate-to-drain capacitance when a CMOS transistor is operated in its triode region but, because of the pinch-off effect, is substantially isolated from the drain when the transistor is operated in its saturation region. Although CMOS transistor capacitance is useful in many applications (e.g., memory circuits), it has typically limited the operating range of CMOS comparators to a value (e.g., 200 MHz) that is significantly lower than that of comparators formed with bipolar junction transistors.
There are many electronic systems (e.g., direct digital synthesizers) in which the use of CMOS transistors enhances the performance of a first portion of the system circuits but degrades performance of a smaller second portion (e.g., the comparator 18). The penalty of degraded performance is often accepted in order to gain the reduction of fabrication costs and system size that are realized when the entire system is fabricated with the same CMOS process. This penalty could be avoided with CMOS comparators that have an improved and competitive operating range.